PARITY CHECKED SHIFT REGISTER COUNTERS

摘要

The present invention relates to a family of parity-checked shift register counters having a counting period not determined by a power of 2 wherein the power is determined by the number of shift register stages. It will be apparent that the range of the counter is effected by the number of stages but not necessarily the actual count. The family of counters is further characterized in that either odd or even parity may be designed into the output pattern of said counter, which parity will be automatically maintained for all binary-bit patterns to produce. The family of counters is further characterized in that they require only N+6 logic circuits wherein there are N shift register stages, four 2-input exclusive ORs and 2 N input AND circuits. The counters are also characterized in that they are self testing. That is, all components are tested for faults in normal operations.