Semiconductor memory device.

摘要

There is disclosed a semiconductor memory device as a multi-port DRAM having split SAM registers. This memory device comprises a RAM section of which memory area is halved into first and second cell arrays (5UC, 5LC) by the value of a specific bit constituting a portion of a column address, a SAM section comprised of first and second registers (61, 62), first second data transfer paths (7U, 7L) for carrying out data transfer from the first and second cell arrays to the first and second registers, respectively, third and fourth data transfer paths (7U, 7L) for shifting data from the first and second cell arrays to the second and first data transfer paths, respectively, and first, second third and fourth transfer controllers (8) are inserted into the first, second third and fourth data transfer paths, respectively, Thus, with this multi-port DRAM, degree of freedom of mapping is improved in constituting a frame buffer. <IMAGE>