发明名称 TESTING SYSTEM FOR INFORMATION PROCESSOR
摘要 PURPOSE:To easily estimate an instruction exerting influence upon an instruction causing defective operation by detecting a minimum instruction string generating discrepancy in execution results between a device to be tested and an instruction level simulator. CONSTITUTION:This testing system is provided with a means 1 for generating a testing instruction string from the 1st instruction up to the j-th instruction prepared at random by using random numbers, a means 4 for mutually comparing results executed by an information processor 2 for testing a testing instruction string consisting of instructions and the instruction level simulator 3, and a means for detecting an minimum instruction string generating discrepancy between the executed results. Consequently, an instruction exerting influence causing defective operation upon a certain instruction can easily be estimated.
申请公布号 JPH04102933(A) 申请公布日期 1992.04.03
申请号 JP19900220244 申请日期 1990.08.22
申请人 NEC CORP 发明人 SANO HIROTAKA
分类号 G06F11/22 主分类号 G06F11/22
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