| 摘要 |
<p>PURPOSE:To permit access to an address even when the address being rewritten exists by executing the erasure/write of data held with a latch means as write data by an instruction execution means. CONSTITUTION:Memory control circuits 18-1 to 18-4 execute the erasure/write operation of the data held with latch circuits 17-1 to 17-4 with corresponding addresses for storage parts 10-1 to 10-4 with corresponding addresses for prescribed time as the write data replying to an erasure/write operation command from a memory control circuit 11. Therefore, an erasure/write instruction accepted by the circuit 11 is executed on all addresses A1-A4 by the circuits 17-1 to 17-4 and the circuits 18-1 to 18-4 with individual address in spite of the common circuit 11 and a data line 15, and the circuit 11 and the line 15 are controlled by one erasure/write instruction only when the instruction is accepted, and the circuit 11 can accept a following instruction after accepting one instruction.</p> |
