发明名称 BUS INTERFACE CHECK SYSTEM
摘要 PURPOSE:To easily detect the area of a trouble by connecting a check circuit provided on a board containing a CPU to an external bus of a bus interface of the board and returning the deciding results of a prescribed pattern as well as a test pattern given from an external bus to an internal bus. CONSTITUTION:When the soundness of a check circuit 113 is confirmed, a test pattern of an internal bus 103 is fetched by the circuit 113 with a READ- DATA signal. If this test pattern is coincident with a prescribed pattern, the READ-DATA signal is applied to the circuit 113. Thus the logical truth is outputted as a check signal for the bus 103. When the soundness of a bus interface 109 is confirmed, a CPU 101 generates a test pattern and writes it into the circuit 113 with the WRITE-DATA and READ-DATA signals. Then the result of collation between the test pattern and the prescribed pattern is outputted. The CPU 101 fetches an external bus check signal which emerges on an external bus 105 and shows the result of collation between both patterns from the bus 103. Thus the true/false value of the bus check signal is observed.
申请公布号 JPH0498555(A) 申请公布日期 1992.03.31
申请号 JP19900216401 申请日期 1990.08.16
申请人 YOKOGAWA HEWLETT PACKARD LTD 发明人 ASADA MUTSUHIKO
分类号 G06F13/00;G06F11/00;G06F11/22 主分类号 G06F13/00
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