| 摘要 |
A multi-sample multi-channel decimator producing a FIR filtering response from 128 digital filter coefficients for 4 independent channels with a decimation ratio of 32, i.e. from 1MHz 1-bit inputs to 32 kHz multibit outputs, splits cyclically the coefficient values in 16 groups of 8, according to the coefficient positions, into 4 ROMs (0, 1, 2, 3). The ROMs are coupled to the 4 multipliers (MULT 0, 1, 2, 3), wherein the coefficient value is multiplied by that of the input bit, through a multiplexer (MUXI) able to cycle through 4 distinct conditions. After the 4 adder accumulators (ACC 0, 1, 2, 3) coupled to the outputs of their respective channel multipliers have, in parallel partially computed output words, each using one sixteenth of the coefficients, the multiplexer rotates these, thereby enabling complete computation in 4 cycles, 4 registers (REG 00, 01, 02, 03) being associated to each adder so as to compute 4 staggered output words simultaneously for each channel. A preferred filtering response can reduce the size of the ROMs. <IMAGE>
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