| 摘要 |
PURPOSE:To achieve partical debugging without repeating a series of arithmetic operations fully, by stopping the arithmetic operation at an optional arithmetic stage. CONSTITUTION:A control memory MT is provided which stores, in a prescribed address, control information commanding arithmetic operation to stop from a keyboard KB, and when the control information is read out by an address counter CUA, the output of the 1st adder AD1 is cut off by turning off a gate GT1, so the contents of a Y register RY and a R register RR are not changed. On the other hand, the output of an output circuit OZ which sends out the increment, reaching a constant value, of an arithmetic result based upon the contents of the R register RR is intercepted by a gate GT1, so that while the contents of the registers RY and RR are held in the states right before that, the arithmetic operation stops. |
