| 摘要 |
<p>PURPOSE:To prevent the fluctuation of a data clock by inputting a digital signal from a transmission line by two different phases, selecting one signal, detecting and outputting a code error, and selecting the other signal, when the code error is detected. CONSTITUTION:When a CMI1 signal is inputted, and a sample clock is generated, based on the CMI1 signal, a delaying circuit 11 outputs a CMI2 signal obtained by delaying the inputted CMI1 signal by a one-period portion of the sample clock, and a frequency dividing circuit 13 outputs a data clock obtained by frequency-dividing the inputted sample clock into 1/2 to an error detector 14 and a decoder. When the CMI1 signal and the CMI2 signal are inputted, a selector 12 selects one of the CMI1 signal or the CMI2 signal in accordance with an error signal inputted from the error detector 14, and outputs it as a CMI3 signal to the error detector 14 and the decoder.</p> |
