发明名称 ARITHMETIC LOGIC UNIT
摘要 PURPOSE:To make a basic operation for processing picture signals only with one instruction by providing an arithmetic logic computing element arithmetic computing element and selector. CONSTITUTION:This arithmetic logic unit is provided with an arithmetic logic computing element 110 which inputs two signals 100 and 101 expressed by the complement of '2' of plural bits, arithmetic computing element 111, and a selector 130 which selects one out of their output signals 120 and 121 and outputs a 1st output signal 122 outputted from the selector 130 and a 2nd output signal 123 outputted from the operator 211. Therefore, the basic operation used for a moving picture encoding process can be executed only by one instruction.
申请公布号 JPH0484317(A) 申请公布日期 1992.03.17
申请号 JP19900199550 申请日期 1990.07.27
申请人 NEC CORP 发明人 YOSHIDA AKIO
分类号 G06F7/50;G06F7/00;G06F7/544;G06F7/57;G06F17/10;G06T1/20 主分类号 G06F7/50
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