TEST MODE SETTING CIRCUIT OF INTEGRATED CIRCUIT,申请号JP19900187651-传众专利搜索

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发明名称	TEST MODE SETTING CIRCUIT OF INTEGRATED CIRCUIT
摘要
申请公布号	JPH0474979(A)	申请公布日期	1992.03.10
申请号	JP19900187651	申请日期	1990.07.16
申请人	NEC IC MICROCOMPUT SYST LTD	发明人	MASUDA KAZUAKI
分类号	G01R31/28;G01R31/3185	主分类号	G01R31/28
代理机构		代理人
主权项
地址

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