发明名称 PARALLEL PROCESSING PROCESSOR
摘要 PURPOSE:To transmit the information at a high speed among plural processors by comparing the reception processor No. of a packet signal with a proper processor No. in order to fetch the packet signal to an operation processing part or to transfer the packet signal to another processor. CONSTITUTION:A data reception processor No. A added to each head part of packet signals P1 and P2 is compared with a processor No. set previously to the processor. When the coincidence is secured between both Nos, the signals P1 and P2 are fetched by an arithmetic part 32 of a parallel processing processor 20 and a prescribed normal processing operation is carried out. If no coincidence is obtained between both Nos, both signals P1 and P2 are never fetched by the part 32 and transferred to another processor as they are from the I/O ports 26 and 28 via an input/output buffer 46. As a result, the memory access time is shortened and the information is transmitted at a high speed among plural processors.
申请公布号 JPH0470953(A) 申请公布日期 1992.03.05
申请号 JP19900176918 申请日期 1990.07.04
申请人 BROTHER IND LTD 发明人 MATSUDA KAZUHIKO
分类号 G06F15/16;G06F15/80;H04L12/70 主分类号 G06F15/16
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