| 摘要 |
PURPOSE:To simplify the circuit constitution by using a phase comparator of a single system to perform the comparison of phase relations between the write and read clock signals which are needed for control of the data reed timing sent from a Doppler buffer included in an asynchronous network of the satellite communication. CONSTITUTION:A buffer 1 is provided together with a buffer 2, a memory circuit 3, an address selection circuit 4, a write address circuit 5, a read address circuit 6, a delay circuit 7, a read pulse control circuit 8, end a buffer 9. The read pulse to be read out of the buffer 2 is simplified with the comparison of phases of a single system carried out between the write and reed pulses by both circuits 7 and 8. That is, the circuit 8 can control the read pulse obtained by a phase comparator of a single system with input of a write clock signal 15 and a read clock signal 18. Thus the hardware scale can be reduced. |
