| 摘要 |
PURPOSE:To enable high-speed multiplication by including a bit train, which is selectively unified to 0, respectively in the outputs of plural partial product generating circuits and multiplying a second digit number smaller than a first digit number at the position of the other bit excepting for the bit train unified to 0. CONSTITUTION:A buffer 4 continuously holds two multipliers Y1 and Y2 and on the other hand, a buffer 3 holds multiplicands X1 and X2. Then, those multiplicands are outputted to respective partial product generating circuits 6a-6n. For calculating the X1Y1, the result is obtained at the low-order 0-48 bits of an adder 11, it is executed concerning the half of total bit number and in that case, a signal 13 to forcedly turn high-order bits to 0 is inputted to the respective partial product generating circuits 6a-6n so as not to exert any adverse influence upon the carry of a code bit. For calculating X2Y2, the result is obtained at the high-order 34-65 bits of the adder 11 and it is executed concerning the half of the total bit number as well. Thus, double-accuracy multiplication is executed in one cycle and high-speed arithmetic is enabled. |
