Semiconductor memory device.

摘要

A semiconductor memory device comprises a memory cell array (101), a column decoding unit (103) supplied with first address data addressing a column of the memory cells for producing a column selection signal, a column switch unit (CS) supplied with the column selection signal for connecting a selected bit line to a corresponding common bit line, a row decoding unit (102) supplied with second address data addressing a row of the memory cells for producing a word line selection signal, a plurality of sensing circuits (LSA) each having an input terminal connected to a corresponding common bit line for detecting a voltage appearing on the common bit line, a plurality of writing circuits (LWA1, LWA2) each connected a corresponding common bit line for writing the data into the addressed memory cell by causing a change in the voltage on the common bit line, and a disconnection circuit (1a, 1b) between the the sensing circuit and the common bit line in each column of the memory cells wherein the disconnection circuit is controlled by the writing circuit such that the sensing circuit is selectively disconnected from the common bit line when the writing circuit writes the data into the memory cell.