发明名称 |
Systolic processor elements for a neural network |
摘要 |
A neural net signal processor provided with a single layer neural net constituted of N neuron circuits which sums the results of the multiplication of each of N input signals Xj(j=1 to N) by a coefficient mij to produce a multiply-accumulate value <IMAGE> thereof, in which input signals Xj(j=1 to N) for input to the single layer neural net are input as serial input data, comprising: a multiplicity of systolic processor elements SPE-1(i=1 to M), each comprised of a two-state input data delay latch; a coefficient memory; means for multiplying and summing for multiply-accumulate output operations; an accumulator; a multiplexor for selecting a preceding stage multiply-accumulate output Sk(k=1 to i-1) and the multiply-accumulate product Si computed by the said circuit; wherein the multiplicity of systolic processor elements are serially connected to form an element array and element multiply-accumulate output operations are executed sequentially to obtain the serial multiply-accumulate outputs Si(i=1 to M) of one layer from the element array.
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申请公布号 |
US5091864(A) |
申请公布日期 |
1992.02.25 |
申请号 |
US19890455141 |
申请日期 |
1989.12.21 |
申请人 |
HITACHI, LTD. |
发明人 |
BAJI, TORU;INOUCHI, HIDENORI |
分类号 |
G06F15/18;G06N3/04;G06N3/063 |
主分类号 |
G06F15/18 |
代理机构 |
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主权项 |
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地址 |
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