发明名称 OPTICAL FIFO MEMORY
摘要 <p>PURPOSE:To decrease a switching time of an optical switch and to uniformize power of an output optical signal by connecting each bit output of a k-bit binary counter to each stage of an 1X(n+1) optical switch in multiple. CONSTITUTION:An optical packet reaching an input optical signal line 1 is fed to a tree type 1X(n+1) optical switch 3. On the other hand, a k-bit binary counter 5 is connected in multiple to 1X2 optical switches 2-1-20n of each stage via optical switch control signal lines 6-1-6-k respectively and the 1X2 optical switches 2-1-20n are switched in response to each bit of the counter 5 and the optical packet is outputted to a designated output position on a time axis. An output of optical delay circuits 7-1-7-n is outputted to an output optical signal line 9 via an (nX1) optical coupler 8. Upon the receipt of the optical packet on the line 1, an optical packet detection circuit 4 supplies a count-up pulse signal to the k-bit binary counter 5.</p>
申请公布号 JPH0458643(A) 申请公布日期 1992.02.25
申请号 JP19900170578 申请日期 1990.06.28
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 SHIMAZU YOSHIHIRO;TSUKADA MASAHITO
分类号 H04Q3/52;H04L12/28;H04L12/931 主分类号 H04Q3/52
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