| 摘要 |
PURPOSE:To stably output a synchronizing clock signal synchronized with a synchronizing trigger signal by comparing the level of a triangular signal with plural reference voltages, generating plural level comparison signals and latching these plural level comparison data and a rectangular signal, which phase is equal to that of the triangular signal, by the synchronizing trigger signal. CONSTITUTION:Output pulse signals C1-C4 of level comparators 5-8 are inputted to a phase measurement and storage circuit 9. This circuit inputs a Q signal of a rectangular output from a VCO 1. The phase measurement and storage circuit 9 is the group of latch circuits to latch the edge (the rise in this case) of the synchronizing trigger signal to be inputted to an input terminal K. When defining the latch output data of the Q output as D0 and defining the latch output data of the signals C3-C4 as D1-D4, those data become the latch output data (phase data) according to the phase range of the synchronizing trigger signal to the triangular signal. This phase data is inputted to an output reset control circuit 10 and an output set control circuit 11. |
