发明名称 TEST METHOD FOR INPUT/OUTPUT PROCESSOR
摘要 PURPOSE:To attain the test of an input/output processor (IOP) in a state where the input/output interruption applied to an answer is held at the IOP side by producing an instruction for the input/output operations in a state where the input/output interruption given from the IOP is inhibited. CONSTITUTION:An initialization part 1 sets a test program of an IOP 23 in a state where the input/output interruptions given from the IOP 23 are inhibited at initialization of a test environment set to a test system. Then plural input/ output operations are instructed to the IOP 23 at one time and in parallel with each other under the task control and by means of a channel program train. The answers held at the side of the IOP 23 are gathered with execution of an IOP answer gathering task 3, for example, and with an instruction of a CPU 21. Based on the contents of these gathered answers, the normalcy of the IOP 23 is confirmed. Thus the IOP 23 can be tested in a state where the input/output interruptions applied to the answers are held by the IOP 23.
申请公布号 JPH0452744(A) 申请公布日期 1992.02.20
申请号 JP19900155643 申请日期 1990.06.14
申请人 NEC CORP 发明人 HIKITA TATSUYA
分类号 G06F11/22;G06F13/00 主分类号 G06F11/22
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