| 摘要 |
<p>A data array processing system comprises a memory system for storing an array of data elements and addressable by a single address, a plural number N of processors (PROC(0)-(15)) capable of processing data elements in parallel, and an address bus. In order to allow parallel access to the memory system where possible, but permit the processors also to access different addresses, each processor is selectable (as PROC(q) - steps 630-640) to supply (step 645) its respective required address (xq, yq) via the address bus to the memory system to access (step 645) the memory, and each non-selected processor is operable to determine (steps 646, 648) whether it requires access to the address (xq, yq) on the bus, and if so to access (step 652) the memory system at the same time as the selected processor (PROC(q)).</p> |
