<p>A CMOS master slice having a plurality of reguraly arranged basic cells improves an integration efficiency by optimizing size and arrangement of MOS transistors in the basic cells. Each of the basic cells comprises a first pair of transistors having gates thereof arranged to parallelly face each other, and a second pair of transistors having gate electrodes shorter in gate width than that of the first pair of transistors and parallel to the gate electrodes of the first pair of transistors. In adjacent basic cells, the gate electrodes of adjacent second transistors are substantially on a line so that a wasteful space is eliminated.</p>
