| 摘要 |
Master processor (5) is connected to the slave processors via bidirectional data channel (10, 13), during fixed time slots of 2ms. Slave processors are supplied with differing timing signals e.g. for data acquisition. Master processor is able to address more than one slave during a given time slot. Communication is in fixed format and is performed according to a matrix wherein each column represents a certain time slot. Columns are organised such that communications with slaves preceding the communication with a specific slave are the same as in all other columns containing a communication with the specific slave. In particular, the slave processors requiring short-interval timing signals are entered on top of the columns, slaves with long-interval signals being entered below these.
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