发明名称 MASTER SLICE SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 A circuit (10) for varying an output current comprises a circuit (12) for generating a controlling signal, a circuit (14) for feeding an output current, and an output terminal (16). The circuit (12) receives two signals; one is a predetermined output signal SOUT of a special-purpose logical circuit (11), and the other is an output signal (internal signal S1) of a predetermined circuit or an external signal S2 from an input terminal. The circuit (12) outputs first and second control signals C1, C2. The circuit (14) comprises two parallel P channel MIS transistors (Tr1, Tr2) between the high potential Vdd of a power supply and the output terminal (16). When the output signal SOUT is at an H level, the transistor Tr2 is in ON-state, and an H-level output of a current value i appears at an output terminal (16). When the output signal SOUT is at an L level and a signal S for changing a current value is at an L level, both the transistors Tr1, Tr2 are in OFF-state, and the output current value is zero. When the output signal SOUT is at the L level and the signal S is at the H level, both the transistors Tr1, Tr2 are in ON-state, and the H-level output of a current value of 2i appears. In this manner, since the current value of the external output XOUT of an H level fed to the output terminal (16) can be set to be i or 2i selectively by the signal S, the consumed electric power can be reduced in correspondence with the environment of the chip used, and the degree of freedom of high-power driving can be increased.
申请公布号 WO9202052(A1) 申请公布日期 1992.02.06
申请号 WO1991JP00975 申请日期 1991.07.18
申请人 SEIKO EPSON CORPORATION 发明人 HIRABAYASHI, YASUHISA;OGUCHI, YASUHIRO;OOKAWA, KAZUHIKO;SAKUDA, TAKASHI
分类号 H01L27/118;H03K17/00;H03K17/16;H03K19/0185 主分类号 H01L27/118
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