| 摘要 |
PURPOSE:To reduce a scale and to improve the computing speed for an arithmetic circuit of a redundant binary form by detecting an overflow based on a carrying signal, the highest-order bit, and a sign bit of the binary data on a redundant binary/binary conversion circuit. CONSTITUTION:A redundant binary adder 1 and a redundant binary/binary conversion circuit 2 are provided with an overflow detecting circuit 4 and a selective circuit 3. The adder 1 outputs a carry C of the addition result and the highest-order bit ZMSB to the circuit 4. Meanwhile the circuit 2 outputs the sign bit ZZsgn of the conversion result to the circuit 4 respectively. The circuit 4 detects a real overflow based on three data C, ZMSB and ZZsgn and outputs the detection result OF to the circuit 3. The circuit 3 selects and outputs an output (s) based on the result OF, the output ZZMAX of a maximum value output circuit 5, the output ZZMIN of a minimum value output circuit 6, and the binary conversion data ZZ. |
