发明名称 MULTIPLEX AND DEMULTIPLEX CIRCUIT
摘要 <p>PURPOSE:To attain the automatic return to the true synchronization by resetting the synchronization protection circuit to implement hunting when number of dissident signal measured by a counter circuit exceeds number of dissidence signals estimated from an error rate of a transmission line regardless that the synchronization protection circuit represents the normal synchronization state. CONSTITUTION:A frame pattern detection circuit 1 compares an input series and a frame synchronization pattern and outputs a coincident signal or a dissident signal. A synchronization protection circuit 2 receives the signal to output an out of synchronism signal. A frame counter circuit 3 receives the dissident signal and the out of synchronism signal and outputs a frame check position pulse. A timer circuit 10 measures a time longer than the frame length, a counter circuit 11 receives dissident signal, the out of synchronism signal and the output signal of the circuit 10, and outputs a synchronization protection reset signal when the out of synchronism signal represents the true synchronization state while the timer is in operation and number of the dissident signal is more than the number estimated from an error rate in the transmission line, resets the synchronization protection circuit 2 to make hunting through an OR circuit 21.</p>
申请公布号 JPH0430636(A) 申请公布日期 1992.02.03
申请号 JP19900134368 申请日期 1990.05.24
申请人 MITSUBISHI ELECTRIC CORP 发明人 MATSUMOTO YASUSHI;KASAHARA MICHIAKI;KITAYAMA TADAYOSHI
分类号 H04J3/04;H04J3/06;H04L7/08 主分类号 H04J3/04
代理机构 代理人
主权项
地址