发明名称 CLOCK EXTRACTION CIRCUIT
摘要 <p>PURPOSE:To reproduce digitally a prescribed clock of a bipolar code even when a code error takes place in part of data by using a clock having a frequency four times that of the prescribed clock so as to obtain a rising position of a positive code and a negative code in a unipolar code and generating a differentiating pulse. CONSTITUTION:A rising position of a positive code AMI+ and a negative code AMI- in a unipolar code U converted by a B/U conversion section 10 is obtained by a clock 4phi CLK having a frequency four times that of the prescribed clock and a pulse is generated by rising differentiating circuits 11, 12 and an OR circuit 3 ORs a ripple carry RC being a carry output of a 1/4 frequency division counter 2 and differentiating pulses P1, P2 outputted from the rising differentiating circuits 11, 12, a value C given in advance is loaded to the 1/4 frequency division counter 2 to start count and the decoder 4 decodes a count of the 1/4 frequency division counter 2 and the falling position of the decoded value is obtained by a falling differentiating circuit 5, from which a differentiating pulse P is generated, A required transmission line clock CLK1 is obtained by generating a repetivive pulse in matching with the period of the differentiating pulse P.</p>
申请公布号 JPH0423636(A) 申请公布日期 1992.01.28
申请号 JP19900129737 申请日期 1990.05.18
申请人 FUJITSU LTD 发明人 OOTSUKA YASUAKI
分类号 H04L25/49;H04L7/00;H04L7/027 主分类号 H04L25/49
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