Programmable inverse time delay circuit.

摘要

An inverse time delay circuit includes an integrator 10 for receiving a signal representative of a voltage or current in an external circuit and a reference signal. The integrator produces a control signal representative of the integral of the difference between the signals. A comparator U2 compares the control signal to a second reference signal to produce an output which changes logic states when the magnitude of the control signals exceeds the magnitude of the second reference signal. A circuit is provided to control the magnitudes of one or both of the reference signals thereby providing control of the instantaneous and/or ultimate trip levels of the circuit. <IMAGE>