| 摘要 |
PURPOSE:To execute the overflow detection processing at a remarkably high speed by providing a means for controlling an inversion output or a non- inversion output to the arithmetic and logic calculating means of data stored in a first storing means in accordance with the value of the most significant bit of a second storing means. CONSTITUTION:Among the products of (m + n) bits in which a multiplication processing by an arithmetic and logic calculating means (ALU) 35 is obtained by the multiplication of data of (m) bits and data of (n) bits, when the data of the upper digit is stored in a first storing means (B register) 32, and the data of the lower digit is stored in a second storing means (M register) 33, a control means (B register output control circuit) 38 controls the inversion output or a non-inversion output to the arithmetic and logic calculating means of the data stored in a first storing means in accordance with the value of the most significant bit of the second storing means, and the arithmetic and logical calculating means sets a zero detecting bit in accordance with the value of the data stored in the first storing means which is subjected to an inversion output or a non-inversion output. In such a manner, the data processor which can detect an overflow in multiplication at a high speed can be obtained. |
