发明名称 VARIABLE LENGTH SHIFT REGISTER CIRCUIT
摘要 PURPOSE:To decrease a setup time of an input signal and to attain high speed operation by selecting the number of selectors through which the input signal passes till the input signal is inputted to a first shift register. CONSTITUTION:M-sets of n-bit shift registers 11 - 1M are used to make nXM (M=1 - M) bit shift. In this case, the number of selectors through which an input data Di passes till the data is inputted to a first shift register is 0 or 1. Moreover, an (n-1) bit shift register 30 and a 1-bit shift register 50 are used to make 1 - 8 bits of shift and in this case, the number of selectors through which the input data Di passes till the data is inputted to the first shift register is always 1. The setup/hold time of the input signal is decreased by making the number of selectors through which an input data Di passes till the data is inputted to a first shift register is 1 or below in this way, thereby attaining high speed circuit operation.
申请公布号 JPH041994(A) 申请公布日期 1992.01.07
申请号 JP19900102597 申请日期 1990.04.18
申请人 FUJITSU LTD 发明人 MORITAKA TETSUO
分类号 G11C19/00 主分类号 G11C19/00
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