| 摘要 |
A data processor having an inner instruction register, a microinstruction register, and microinstruction decoder for decoding the microinstruction stored in the microinstruction register, and a data expansion section for expanding data bits stored in source and destination registers among general purpose registers when designated by an inner instruction in which the bit lengths of data to be processed can be designated by an inner instruction, a microinstruction for performing the operation of data having same contents but different bit lengths can be made common, thereby reducing the number of steps of the microprograms.
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