发明名称 PROCEDE DE FABRICATION D'UN TRANSISTOR DANS LEQUEL LE NIVEAU DE CONTRAINTE APPLIQUE AU CANAL EST AUGMENTE
摘要 Method of manufacturing a transistor on a layer made of a first crystalline semiconducting material to make a channel, deposited on a dielectric layer, the method including the following steps: epitaxial growth of zones made of a second semiconducting material on the layer made of a first crystalline semiconducting material, so as to form source and drain blocks with the layer made of a first crystalline semiconducting material on each side of the channel, the second semiconducting material having a lattice parameter different from that of the first semiconducting material, in-depth amorphisation of part of zones made of a second semiconducting material so as to keep only one layer of second crystalline semiconducting material on the surface of the source and drain blocks, and amorphisation of zones of the layer made of a first semiconducting material located under zones made of a second semiconducting material, recrystallisation of the source and drain blocks such that the second semiconducting material imposes its lattice parameter on the source and drain zones.
申请公布号 FR3023972(B1) 申请公布日期 2016.08.19
申请号 FR20140056936 申请日期 2014.07.18
申请人 COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES 发明人 BATUDE PERRINE;MAZEN FREDERIC;REBOH SHAY;SKLENARD BENOIT
分类号 H01L21/335;H01L27/085 主分类号 H01L21/335
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