Techniques providing high-k dielectric metal gate CMOS

摘要

A semiconductor device includes a dielectric layer on a substrate, a P-type transistor having a first gate stack embedded in the dielectric layer, and an N-type transistor having a second gate stack embedded in the dielectric layer. The first gate stack includes a first metal gate electrode, a first gate dielectric layer underlying the first metal gate electrode, and a first cap layer between the first gate dielectric layer and the first metal gate electrode. The second gate stack includes a second metal gate electrode, a second gate dielectric layer underlying the second metal gate electrode, and a second cap layer between the second gate dielectric layer and the second metal gate electrode. The first and second gate stacks are adjacent, and the first and second metal gate electrodes are separated from each other by the first and second cap layers.

主权项

1. A semiconductor device comprising:
a dielectric layer on a substrate; a P-type transistor having a first gate stack embedded in the dielectric layer; and an N-type transistor having a second gate stack embedded in the dielectric layer; wherein the first gate stack includes:
a first metal gate electrode;a first gate dielectric layer underlying the first metal gate electrode and covering at least a sidewall of a trench; anda first cap layer between the first gate dielectric layer and the first metal gate electrode; and wherein the second gate stack includes:
a second metal gate electrode;a second gate dielectric layer underlying the second metal gate electrode and covering at least a sidewall of the trench; anda second cap layer between the second gate dielectric layer and the second metal gate electrode; and further wherein the first and second gate stacks are adjacent, and the first and second metal gate electrodes are separated from each other by the first and second cap layers, and the first gate dielectric layer and the second gate dielectric layer form a continuous, substantially planar top surface extending underneath both the first metal gate electrode and the second metal gate electrode.