发明名称
摘要 PURPOSE:To reduce the capacity of the register by using the output data equivalent to one block plus the data equivalent to the preceding one block when the reproduction data is corrected via the PCM recorder/reproducer and the like, and thus to simplify the constitution of the correction device. CONSTITUTION:Both n+1st block and the NO.n block are read out simultaneously from RAM1 in the form of the 1st and 2nd output data Sd1 and Sd2 respectively. And in case an error takes place in the No.i word Di,n+1 of the n+1st block, the error is detected by FF16. Then decision bit Fi,n+1 of the corresponding word becomes 1, which is then supplied to control circuit 12. Data Sd1 undergoes the serial arithmetic process through exclusive OR gate 17 and 1-word shift register 18 and via control signals P1-P6 given from circuit 12. Thus correct data Di,n+1 is formed, stored in 1-word shift register 21 and replaced with error data (Di,n+1) emerging again to data Sd2 through selector 15 to be delivered through terminal 23.
申请公布号 JPH0379890(B2) 申请公布日期 1991.12.20
申请号 JP19780084434 申请日期 1978.07.11
申请人 SONY CORP 发明人 ODAKA KENTARO
分类号 G06F11/10;G11B20/18;H03M13/00 主分类号 G06F11/10
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