发明名称 MEMORY ACCESS SYSTEM
摘要 PURPOSE:To reduce the burden of a microprocessor or the like by reading surrounding bits (groups) related to a designated bit, and dispatching those bits to the microprocessor or the like in the state of rounding them. CONSTITUTION:A CPU 1 is a central processing unit and exchanges the data of an address to be designated by an address bus 2 through a data bus. A P.ROM 4 is a ROM storing programs, and the CPU 1 successively reads and executes the programs in the P.ROM 4. On the other hand, a C.ROM 5 is a character ROM storing picture data such as character font patterns or the like. A RAM 6 is used as the work area, etc., of the CPU 1. A bit data read circuit BLK 7 is a part as the feature of this invention. A register in this bit data read circuit BLK 7 is made accessable from the CPU 1, and the data on the C.ROM 5 or the RAM 6 can be read out through the address bus 2 and the data bus 3.
申请公布号 JPH03291767(A) 申请公布日期 1991.12.20
申请号 JP19900093141 申请日期 1990.04.10
申请人 CANON INC 发明人 SUGIYAMA KAZUHIKO
分类号 G06F12/00;G06F12/02;G06T1/60;G06T5/20 主分类号 G06F12/00
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