发明名称 INTEGRATED CIRCUIT FOR DISCRETE TYPE COSINE CONVERSION BY UTILIZING NEURO-NETWORK
摘要 <p>PURPOSE: To improve the calculation rate by using a circuit utilizing a neural network with a parallel processing characteristic for a part necessitating a long period at the time of performing the discrete cosine transformation. CONSTITUTION: This circuit is provided with a multiplier 20 utilizing a neural network for multiplying the output of a cosine term processing part 10 and an input value from an external circuit, an adder 30 utilizing the neural network for summing the product value and a value latched by a first latching part 50, a subtracter 40 utilizing the neural network for subtracting a specified number of bits of the exponent part by a specified constant so as to divide the final output value by N/2 and a second latch part which is reset when an underflow is generated and latching the input signal from the subtracter 40 and the first latch part 50 according to a second clock signal to maintain an output value. Namely, this integrated circuit for discrete cosine transformation uses a general digital circuit, the basic circuit of a neural network conception, and the like, and at the time of processing the discrete cosine transformation, a part necessitating a long period is processed by means of a circuit utilizing a neural network with a parallel processing characteristic. Thereby the calculation rate is improved.</p>
申请公布号 JPH03286366(A) 申请公布日期 1991.12.17
申请号 JP19900222348 申请日期 1990.08.23
申请人 SAMSUNG ELECTRON CO LTD 发明人 TEI KOUSEN;YANAGI NARIMITSU
分类号 G06F15/18;G06F17/14;G06N3/00;G06N3/063;G06N99/00 主分类号 G06F15/18
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