| 摘要 |
PURPOSE:To lessen a bipolar transistor which composes a memory cell in collector current in operation by a method wherein the emitter of the bipolar transistor is lessened more in area as compared with a base contact so as to change a collector current Ico, and an avalanche multiplication phenomenon induced at a junction between a collector and a base is controlled. CONSTITUTION:An N<+>-type forcedly plunged layer 22 is provided onto the surface of a P<->-type silicon substrate 21 so as to lessen a collector in resistance, and furthermore a P<->-type epitaxial silicon layer 23 is provided thereon. Phosphorus is introduced into the P<->-type silicon layer 23 to form an N-type well 24. A field oxide film 25 is formed on the surface, a polysilicon 27 is provided onto an opening provided between the oxide films 25 on a collector lead-out layer 26 deep enough to reach to the N<+>-type forcibly plunged layer 22, and a P<->-type base region 28 is provided to another opening. An N<+>-type emitter region 29 is formed formed on a part of the P<->-type base region 28, a thin oxide film 30 is formed on the surface of the substrate, and furthermore a polysilicon 32 is formed through the intermediary of the window of a CVD SiO2 film 31. A P<+>-type layer 33 (outer base) is provided adjacent to the P<->-type base region 28. |
