| 摘要 |
<p>The semiconductor memory device according to the present invention have a memory cell array consisting of a plurality of memory cells provided in array form and a plurality of bit lines and word lines connected respectively to the plurality of memory cells, an I/O lines consisting of a first wiring and a second wiring connected to a predetermined number of bit lines out of the plurality of the bit lines via a selection circuit, and a clamping circuit which is activated at the time of read and includes first means that connects the first wiring and the second wiring when the potential of the first wiring exceeds the potential of the second wiring by more than a predetermined voltage value, and second means that connects the first wiring and the second wiring when the potential of the second wiring exceeds the potential of the first wiring by more than the predetermined voltage value. With the construction as described above, even when a potential drop is generated in the I/O lines during the transition period, a marked drop in the potential of one of the wirings can be prevented by the clamping operation between the two wirings that constitute the I/O lines. Accordingly, it is possible to prevent the destruction of data in the memory cells, and to enhance the reading speed of the next data because of the small value of the potential drop of the wiring. <IMAGE></p> |
