| 摘要 |
PURPOSE:To surely eliminate noise whose width is set to a specified pulse width or below at a fast speed by providing a noise elimination pulse generating circuit, a delay circuit and a logic arithmetic circuit. CONSTITUTION:When a regular keying pulse signal (a) is inputted as an input signal to the keying pulse processing circuit, a regular keying pulse signal (c) delayed by a delay circuit 7 and a noise eliminating pulse signal (b) with a prescribed pulse width narrower than the pulse width of the signal (a) synchronously with the signal (a) are synthesized at a logic arithmetic circuit 8, in which the coincident pulse is eliminated. Thus, a pulse signal (d) corresponding to the signal (a) is outputted, and on the other hand, when a noise whose pulse width is less than a prescribed pulse width resulting from the subtraction of a prescribed delay time of the delay circuit 7 from the prescribed pulse width of the noise eliminating pulse signal (b) is inputted, the noise delayed by the delay circuit 7 is included in the noise elimination pulse signal (b) with a prescribed pulse width and erased. Thus, the noise whose pulse width is less than the the inputted and specified pulse width is surely eliminated at a fast speed. |
