| 摘要 |
<p>PURPOSE:To obtain a negative voltage larger than a potential difference between a power supply potential and a ground potential by a method wherein the wells of a third and a fourth transistor are connected to a source or a drain in a switching manner respectively, and an input voltage is applied onto the source of the fourth transistor. CONSTITUTION:If clock signals are applied to the gates of transistors QP1, QN1-QN3, the transistors QP1 and QN3 are turned ON and the transistors QN1 and QN2 are turned OFF when the clock signal C is kept at an H level, a voltage of VDD is applied to the positive electrode of a capacitor C1, and an input voltage of VIN is applied to the negative electrode. Therefore, the charged voltage VCI of the capacitor C1 is represented by a formula, VCI= VDD-VIN. At following timing, the transistors QP1 and QN3 are turned OFF and the transistors QN1 and QN2 are turned ON, the positive electrode of the capacitor C1 is switched to a voltage of VSS and the voltage of the negative electrode is made to decrease to a voltage lower than VSS by VCI, so that an output voltage of VOUT is represented by a formula, VOUT=-(VDD-VIN). Therefore, the input voltage VIN is represented by a formula, VDD>=VIN>=VOUT.</p> |
