| 摘要 |
PURPOSE:To attain addition/subtraction of a floating point data in high speed by processing in parallel the post-processing such as the detection of exception event and a conditional code generation processing independently of the addition/ subtraction of the mantissa and the correcting processing of the exponent. CONSTITUTION:The exponent part of input data 1, 2 is inputted to a comparator 1, a shift control data is fed to shift circuits 2, 3 and fed to an ineffective digit detecting shift amount calculating section 9 in addition to an adder 4 so as to detect the ineffective digit and the shift amount. The shift amount is fed to a shift circuit 6, an exponent correction circuit 7 and an exception even detection and condition code forming section 10 so as to execute in parallel the setting of the condition code CC in parallel with the subtraction/addition of the mantissa at the adder 4. When the shift amount is calculated at a shift amount calculating section 9 of the shift circuit 6, the shift operation is conducted to normalizethe ineffective digit of the mantissa generated at the adder 4. The exponent correcting circuit 7 subtracts the shift amount required for the normalization obtained by the shift amount calculating section 9 in the order of the larger exponent part so as to form the exponent part of the final output data. |
