ECL FREQUENCY DIVIDING CIRCUIT

摘要

PURPOSE:To suppress self-oscillation specific to a frequency dividing circuit while the difference of an input DC offset current is minimized by selecting the size of the emitter of a transistor(TR) through which a current for a slave amplifier is supplied to the size of a multiple of (GO+1)/(GO-1) of the TR of a master amplifier or above. CONSTITUTION:The size of the emitter of a TR through which a current for a slave amplifier is supplied in a middle-stage input clock amplifier stage is set to the size of a TR of a master amplifier of middle-stage input clock amplifier stage as a multiple of (GO+1)/(GO-1) (GO is a DC gain of a data amplifier). Thus, the free-run operation of a frequency dividing circuit is suppressed without increasing number of components while the deterioration in the minimum input sensitivity and of the highest operating frequency characteristic is minimized.