| 摘要 |
<p>PURPOSE:To prevent received data from being omitted by controlling the sequence storing the received data into reception buffer memory with a hardware independent of a central processing unit(CPU). CONSTITUTION:A reception queue 24 and an idle reception buffer queue 25 are provided on a reception interface part 21, connected to an address control part 22 and also connected to a reception processing control part 16 by a local bus 27. At the reception processing control part 16 a processing waiting block number is fetched from the reception queue 24 through the local bus 27, and an idle empty block number is supplemented to the idle reception buffer queue 25. A block number '0' is fetched here, but the new idle block number is not supplemented. Afterwards, a reception interruption signal 28 from an interruption signal output part 26 is reset, and a reception completion informing signal 19 is transmitted to the CPU 11. Thus, the received data is prevented from being omitted.</p> |
