| 摘要 |
<p>An operational amplifier employs split collector transistors (Q1, Q2) for the input differential pair. Through a fractional collector of the input transistors (Q1, Q2) a fraction of the currents (1/4) flowing through the two branches of the input differential stage is derived and by means of two complementary mirrors (Q9 - Q12) having a sufficiently high, combined mirror-ratio, this current, which is proportional to the amplitude of the signal present across the input terminals of the amplifier, is fed as a biasing current (I) to the input node of the output buffer stage (Qx, Qy) of the amplifier in order to enhance the slew-rate behaviour by ensuring a fast charging of the frequency compensation capacitance (Cc) during a transient condition while maintaining a low power dissipation under small signal steady state conditions. <IMAGE></p> |
