| 摘要 |
<p>A circuit for monitoring digital electrical signals which counts events, compares the event count to a threshold value, generates an equal value signal when the threshold is attained and indicates the time elapsed between an initial value and the generation of the equal value signal. The event counter is automatically cleared or reset upon a user enabled automatic clear logic enabling signal. The circuit is preferably configured as a chip employing GaAs Schottky diode field effect transistor logic (SDFL) gates.</p> |
