发明名称 PACKAGE FOR INTEGRATED CIRCUIT
摘要 <p>PURPOSE:To reduce the fluctuation of GND potential even when output terminals, etc., are operated simultaneously, and to prevent a malfunction by mounting a plurality of signal pins on each side face section, connecting the signal pins to pads for signals in a chip on the inside, installing a conductive plate to a base section, connecting a plurality of projecting sections to the upper section of the conductive plate and connecting the conductive plate to pads for GND in the chip from the projecting sections. CONSTITUTION:A plurality of signal pins 2 from each side face are set up in a molding package 1, and bonded with the signal pads of a chip 5 by bonding wires 6. A conductive plate 3 is fitted to a base, a plurality of projecting sections 4 are connected to the conductive plate 3, and bonded with the GND pads of the chip 5 by the bonding wires 6 from the upper sections of the projecting sections 4. Accordingly, the chip 5 is connected to GND by the conductive plate from the base section, thus reducing impedance.</p>
申请公布号 JPH03270063(A) 申请公布日期 1991.12.02
申请号 JP19900070167 申请日期 1990.03.19
申请人 NEC CORP 发明人 IKEDA KATSUJI
分类号 H01L23/50 主分类号 H01L23/50
代理机构 代理人
主权项
地址