| 摘要 |
PURPOSE:To reduce hardware amount by a method wherein a chip is specified by analyzing the positional relation between pad candidate points extracted by searching the inside of a screen, and positioning is performed on the basis of the position of a pad characterizing the chip. CONSTITUTION:A bonding pad 2 of a chip 1 on a wafer is used as a pattern for calculating the correlation of a small region; pad candidate points are extracted by searching a screen; the chip 1 is specified by analyzing the positional relation between pad candidate points; the positioning of the chip 1 is performed on the basis of the position of the pad 2 characterizing the chip 1. That is, positioning is performed by noticing a pad, and the normal correlation may be obtained only about a small master pattern, so that the normal correlation value can be obtained about each area of the whole screen by using a comparatively simple hardware. Thereby hardware amount can be reduced. |
