发明名称 LOGIC GATE CIRCUIT AND ITS EVALUATING METHOD
摘要 <p>PURPOSE:To eliminate the need for a pulse generator by connecting a circuit for positive feedback between an input and an output terminal, turning on the circuit for positive feedback in test mode and evaluating whether logic is true or false from whether oscillation occurs or not, and evaluating a delay time with the oscillation frequency. CONSTITUTION:One input terminal 12 and the output terminal 14 of the logic gate circuit 10 are connected to each other by the circuit 18 for positive feedback which consists of inverters 15 and 16 and a transmission gate 17, which controls the connection and disconnection of the circuit 18 with and from the circuit 10. For the evaluation, and the input terminals 11 and 13 are grounded and applied with a level 'L', a source voltage is applied to a control voltage to applies a level 'H'. In this test mode, the circuit 18 is connected between the input and output of the circuit 10 to constitute a ring oscillator. The inverter 15 makes the number of stages of the ring 15 odd, so this inverter is not necessary when there are an odd number of stages present between the input and output of the circuit 10. Consequently, when the logic of the circuit 10 is true, oscillation is started, so its frequency is detected to find the delay time between the input and output from a specific expression.</p>
申请公布号 JPH03262986(A) 申请公布日期 1991.11.22
申请号 JP19900061589 申请日期 1990.03.13
申请人 NEW JAPAN RADIO CO LTD 发明人 TOSUMI YASUKAZU;GOTO MASAAKI
分类号 G01R31/317;H03K19/00 主分类号 G01R31/317
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