发明名称 |
WAFER SCALE INTEGRATED CIRCUIT |
摘要 |
A wafer scale integrated circuit wherein at least one of a plurality of functional blocks (2) formed on a semiconductor wafer (1) has its internal defects repaired and has an area which is at least 2.3 cm<2>. The integrated circuit permits the use of a functional block having an area that is much greater than that of the conventional blocks. Therefore, the total length of wirings among the blocks can be shortened to simplify the complex wiring process, the total number of wiring layers can be reduced, and the signal propagation delay time can be shortened, too, making it possible to realize a high packaging density with low redundancy. |
申请公布号 |
EP0308726(A3) |
申请公布日期 |
1991.11.21 |
申请号 |
EP19880114614 |
申请日期 |
1988.09.07 |
申请人 |
HITACHI, LTD. |
发明人 |
MASAKI, AKIRA;YASUNAGA, MORITOSHI;MIZUISHI, KENICHI;MUKAI, KIICHIRO;ITOH, HIROYUKI |
分类号 |
H01L23/522;G11C29/00;H01L21/768;H01L21/82;H01L23/528;H01L27/118;(IPC1-7):H01L27/02 |
主分类号 |
H01L23/522 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|