Serial data transmission procedure - using start=stop principle in async. digital bus system

摘要

In a receiver the time slots (T3,T4) of the individual bits of a message are fixed not only by the receiving time of the climbing flank (VFI) of the start bit and the bit length, but also by the time between the time slot (T2) of the stop bit and the climbing flank (VF1) of the start bit. If this time period falls below a minimal value the time slot is delayed to a mid point (TM3). If it exceeds a max. value the time slot is advanced. USE/ADVANTAGE - Bus systems for computer coupling and automating systems with repeaters. Prevents errors in data transmission or reproduction.