SYSTEM FOR PREPARING INSTRUCTIONS FOR INSTRUCTION PARALLEL PROCESSOR AND SYSTEM WITH MECHANISM FOR BRANCHING IN THE MIDDLE OF A COMPOUND INSTRUCTION

摘要

An instruction processor system for decoding compound instructions created from a series of base instruction (21) of a scalar machine, the processor generating a series of compound instruction (33) with an instruction format text having appened control bits in the instruction format text enabling the execution of the compound instruction format text in said instruction processor with a compounding facility (42) which fetches and decodes compound instructions which can be executed as compounded and single instructions by the arithmetic and logic units (26) of the instruction processor while preserving intact the scalar execution of the base instructions of a scalar machine which were originally in storage. The system nullifies any execution of a member instruction unit of a compound instruction upon occurrence of possible conditions, such as branch wich would affect the correctness of recording results of execution of the member instruction unit portion based upon the interrelationship of member units of the compound instruction with other instructions. The resultant series of compounded instructions generally executes in a faster manner than the original format which is preserved due to the parallel nature of the compounded instruction stream which is executed.