| 摘要 |
<p>The device is provided with a counter (21) for counting, during a frame suppression signal, the line synchronisation signals applied to its clock input (CP). The counting-enable input (CEP) of the counter receives a signal whose duration corresponds to the duration of five half-lines. The counter starts from zero again when it has counted five signals, whilst then indicating on a specific output (TC) that the count has reached five, and this output (TC) is connected to a logic circuit (14 to 18) which, at the end of each frame suppression interval, delivers a binary signal (19) which remains unchanged when the counter's counting digit has reached five and which is inverted in the contrary case. This binary signal controls a demodulator for adapting it to the polarity. Application: television receivers, either multistandard, or in which it is necessary to ascertain the polarity of a video signal which is inverted with respect to the normal signal of a given broadcasting standard, for example for the purpose of intensifying a scrambling. <IMAGE></p> |
